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How big is your LRA?
This is a guest post written by Matt Burns, who’s on the technical marketing team at Avnet Electronics. It’s the first in a new multi-author Haptics series we’ll be running here on Analog Wire....
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Get Connected: SerDes XAUI to SFI design
Welcome back to the Get Connected blog series here on Analog Wire! In the previous Get Connected blog post, SerDes Interfaces, we examined the OSI model and the different layers that make up the...
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Timing is Everything: How to measure additive jitter
Welcome to the first blog in our new Timing is Everything series! In this series, you will find all your clock questions and needs addressed by our TI clock experts. I will be kicking off this new...
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Complex translation made simple
This post was co-written by Dave Long and Jose GonzalezConnecting devices to one another has gone from a cool idea to a must-have. From activity trackers to smart homes, we see the need for more data...
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Timing is Everything: Understanding PLL loop filter response
Welcome back to Timing is Everything! Last time in our series, we covered how to measure additive jitter. Today, I will be discussing phase lock loop (PLL) systems and how to understand PLL loop filter...
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JESD204B: Understanding the protocol
I’ve learned a lot about the JESD204B interface standard while designing systems with our latest analog-to-digital converters (ADCs) and digital-to-analog converters (DACs), which use this protocol to...
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Clocking sampled systems to minimize jitter
As many of you know, jitter (which is clock edge uncertainty) is a bad thing that leads to increased noise and degradation of a data converter’s ENOB. For example, if we have a system that requires an...
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A Reference for Voltage References
Did you know that at least one voltage reference is used in almost every application? This is because a reference point is typically required somewhere inside the signal chain of a system. Voltage...
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Part 1 - Avoid common missteps with the common mode
Have you noticed how differential signaling is becoming more and more dominant in high performance signal paths? Differential signaling offers several advantages! I’ve been thinking about the fact...
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Get Connected: Interfacing between LVPECL, VML, CML, LVDS, and sub-LVDS levels
Welcome back to the Get Connected blog series here on Analog Wire! In the previous Get Connected blog post, SerDes XAUI to SFI design, we took an in-depth look at using the TLK10232 in a XAUI to SFI...
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JESD204B: How to bring up your link
In my previous post, Understanding the protocol, I took a high-level functional look at the three states within the JESD204B protocol that are critical to establish a valid data link between the TX and...
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Timing is Everything: Jitter specifications
Welcome back to Timing is Everything! Last time we covered Understanding PLL loop filter response. Today, I will be helping you learn how to better understand the variety of jitter specifications. As...
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Minimize your current, pick a sweet spot!
Pick any CMOS or JFET amplifier and you’ll get the lowest possible input bias (Ib) current, right?Not so fast. If you mean low Ib compared to that of bipolar, then yes. But if you mean sub 10pA, there...
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Timing is Everything: I need a clock, can you help?
Welcome back to our Timing is Everything clock series! Today I will be covering how to select the clock or timing IC that best fits your application.It’s a fair question to ask: “Is there more to...
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Inductive Sensing: Five-minute sensor coil design
Did you know you can design a PCB coil for inductive sensing in five minutes with WEBENCH®? If you are considering using an inductance-to-digital converter, like the LDC1000, but are concerned about...
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How design your system like a true pirate engineer
Yar Mateys! I’ve been told today is “Pirate Appreciation Day,” or as you land lubbers call it, “Talk Like a Pirate Day.” A day where all those who sail the seven seas stop and raise a mug of grog and...
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Addressing 100G Growing Pains
If you strip enough layers off of your optical networking system, you will get to the physical layer― the nuts and bolts of the backbone of communication. The receive optical sub assembly (ROSA) and a...
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JESD204B: Determining your link configuration
If you’ve been following my JESD204B series, you have a basic understanding of the protocol and signaling required to establish a link between a JESD204B transmitter and receiver. We can now move on to...
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Haptics to go: Wireless tool easily prototypes tactile effects
In a broad sense, “haptics” refers to the feeling of touch. It could be a simple vibration feedback from any human-machine interface, like a smartphone, to recreating surfaces and textures on a tablet...
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4-20 mA Industrial Loops Made Easy
If you’ve ever sat down and designed (from scratch) a discrete 4-20 mA control loop, you may have found it a bit more challenging than it appeared. First, current loop communication (both analog and...
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